P2.5 64x64 1/32 MY9862
64x64, 1/32 scan, MY9862, 2.5 mm pitch, rcvbp
- maker
- Adafruit
- product
- 64x64 RGB LED Matrix - 2.5mm Pitch [1/32 Scan]
Download
Module
entry
- file
- config/panels/mined/64x64-32s-my9862.toml
- pitch
- 2.5 mm
- status
- generates
- origin
- mined
- vendor files
- 6
- agreement
- 1
- vendors
- Colorlight
- examples
- CD-P3.0(1515)-64X64-SM16208+5166-32S-SY-8.85.rcvbp CD-P3.0(2121)-64X64-SM16208+5166-32S-SY-8.85.rcvbp CD-P3.0(1515)-64X64-SM16208+5166-32S-SY.rcvbp
- notes
- Matched to a product on sale at medium confidence: Same generic 64x64/32-scan module as sibling rows; chip not stated on page.
chip
- name
- MY9862 (mined)
- library
- config/chips/mined/my9862.toml
spec
- name
- 64x64-32s-my9862
module
- width
- 64
- height
- 64
- scan
- 32
- line_dir
- 0
- data_groups
- 1
- serial_clock
- 7
screen
- width
- 64
- height
- 64
Wiring
mapping
- reversed_groups
- true
- reversed_lines
- false
- block
- 64
boot
- arm_at_boot
- true
Timing
current
- gains
- [1, 5, 5, 43]
- percent
- [0.1, 0.1, 0.1]
config/panels/mined/64x64-32s-my9862.toml
# generated by scripts/corpus-mine.py; regenerate rather than edit name = "64x64-32s-my9862" [meta] status = "generates" origin = "mined" sources = 6 agreement = 1.00 examples = ["CD-P3.0(1515)-64X64-SM16208+5166-32S-SY-8.85.rcvbp", "CD-P3.0(2121)-64X64-SM16208+5166-32S-SY-8.85.rcvbp", "CD-P3.0(1515)-64X64-SM16208+5166-32S-SY.rcvbp"] vendors = ["Colorlight"] maker = "Adafruit" product = "64x64 RGB LED Matrix - 2.5mm Pitch [1/32 Scan]" pitch_mm = 2.5 url = "https://www.adafruit.com/product/3649" image = "https://assets.receiverproxy.com/images/panels/64x64-32s-my9862.jpg" image_source = "Adafruit product photo" notes = "Matched to a product on sale at medium confidence: Same generic 64x64/32-scan module as sibling rows; chip not stated on page." [module] width = 64 height = 64 scan = 32 line_dir = 0 data_groups = 1 serial_clock = 7 [screen] width = 64 height = 64 [chip] library = "config/chips/mined/my9862.toml" [current] gains = [1, 5, 5, 43] percent = [0.1, 0.1, 0.1] [mapping] reversed_groups = true reversed_lines = false block = 64 [boot] arm_at_boot = true