P2.5 64x64 1/16 MBI5124N
64x64, 1/16 scan, MBI5124N, 2.5 mm pitch, rcvbp
- maker
- led-card.com
- product
- P2.5 outdoor LED Module acute angle
Download
Module
entry
- file
- config/panels/mined/64x64-16s-mbi5124n.toml
- pitch
- 2.5 mm
- status
- generates
- origin
- mined
- vendor files
- 6
- agreement
- 1
- vendors
- Colorlight
- examples
- P3.91-16S-5124DPWM-64X64-250X250-HL-3.0.rcvbp P3.91-1921-16S-HL3.0-MBI5124N.rcvbp P3-16S-5124DPWM-64X64-192X192-KSL-V3.0.rcvbp
- notes
- Matched to a product on sale at medium confidence: Same generic 64x64/16-scan module as sibling rows; chip not stated on page.
chip
- name
- MBI5124N (mined)
- library
- config/chips/mined/mbi5124n.toml
spec
- name
- 64x64-16s-mbi5124n
module
- width
- 64
- height
- 64
- scan
- 16
- line_dir
- 0
- data_groups
- 0
- serial_clock
- 8
screen
- width
- 64
- height
- 64
Wiring
mapping
- reversed_groups
- true
- reversed_lines
- false
- block
- 64
boot
- arm_at_boot
- true
Timing
current
- gains
- [43, 43, 43, 43]
- percent
- [0.1, 0.1, 0.1]
config/panels/mined/64x64-16s-mbi5124n.toml
# generated by scripts/corpus-mine.py; regenerate rather than edit name = "64x64-16s-mbi5124n" [meta] status = "generates" origin = "mined" sources = 6 agreement = 1.00 examples = ["P3.91-16S-5124DPWM-64X64-250X250-HL-3.0.rcvbp", "P3.91-1921-16S-HL3.0-MBI5124N.rcvbp", "P3-16S-5124DPWM-64X64-192X192-KSL-V3.0.rcvbp"] vendors = ["Colorlight"] maker = "led-card.com" product = "P2.5 outdoor LED Module acute angle" pitch_mm = 2.5 url = "https://www.led-card.com/p2-5-outdoor-acute-angle-module.html" image = "https://assets.receiverproxy.com/images/panels/64x64-16s-mbi5124n.jpg" image_source = "led-card.com product photo" notes = "Matched to a product on sale at medium confidence: Same generic 64x64/16-scan module as sibling rows; chip not stated on page." [module] width = 64 height = 64 scan = 16 line_dir = 0 data_groups = 0 serial_clock = 8 [screen] width = 64 height = 64 [chip] library = "config/chips/mined/mbi5124n.toml" [current] gains = [43, 43, 43, 43] percent = [0.1, 0.1, 0.1] [mapping] reversed_groups = true reversed_lines = false block = 64 [boot] arm_at_boot = true