64x32 1/16 ICN2053
64x32, 1/16 scan, ICN2053, rcvbp
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Module
entry
- file
- config/panels/mined/64x32-16s-icn2053.toml
- status
- generates
- origin
- mined
- vendor files
- 8
- agreement
- 1
- vendors
- Colorlight
- examples
- P5-16S-64X32-2053+2012-5.88.rcvbp P3.91-64x64-16S-V1.0-3960Hz-128x128-ICN2053.rcvbp P4+6353+64X32-16S+75E.rcvbp
chip
- name
- ICN2053 (mined)
- library
- config/chips/mined/icn2053.toml
spec
- name
- 64x32-16s-icn2053
module
- width
- 64
- height
- 32
- scan
- 16
- line_dir
- 0
- data_groups
- 0
- serial_clock
- 15
screen
- width
- 64
- height
- 32
Wiring
mapping
- reversed_groups
- true
- reversed_lines
- false
- block
- 64
boot
- arm_at_boot
- true
Timing
current
- gains
- [230, 230, 230, 43]
- percent
- [0.1, 0.1, 0.1]
config/panels/mined/64x32-16s-icn2053.toml
# generated by scripts/corpus-mine.py; regenerate rather than edit name = "64x32-16s-icn2053" [meta] status = "generates" origin = "mined" sources = 8 agreement = 1.00 examples = ["P5-16S-64X32-2053+2012-5.88.rcvbp", "P3.91-64x64-16S-V1.0-3960Hz-128x128-ICN2053.rcvbp", "P4+6353+64X32-16S+75E.rcvbp"] vendors = ["Colorlight"] [module] width = 64 height = 32 scan = 16 line_dir = 0 data_groups = 0 serial_clock = 15 [screen] width = 64 height = 32 [chip] library = "config/chips/mined/icn2053.toml" [current] gains = [230, 230, 230, 43] percent = [0.1, 0.1, 0.1] [mapping] reversed_groups = true reversed_lines = false block = 64 [boot] arm_at_boot = true