64x128 1/64 LS9929
64x128, 1/64 scan, LS9929, rcvbp
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Module
entry
- file
- config/panels/mined/64x128-64s-ls9929.toml
- status
- generates
- origin
- mined
- vendor files
- 17
- agreement
- 0.77
- vendors
- Colorlight
- examples
- P1.875-128x64-64S-9929+9739-5.0-75B.rcvbp P1.875_128x64_64s-9929+9739.rcvbp P2.5-128x64-64S-9929+9737(mini)-3.15-_128x1024-75E_.rcvbp
chip
- name
- LS9929 (mined)
- library
- config/chips/mined/ls9929.toml
spec
- name
- 64x128-64s-ls9929
module
- width
- 64
- height
- 128
- scan
- 64
- line_dir
- 0
- data_groups
- 0
- serial_clock
- 14
screen
- width
- 64
- height
- 128
Wiring
mapping
- reversed_groups
- true
- reversed_lines
- false
- block
- 64
boot
- arm_at_boot
- true
Timing
current
- gains
- [43, 43, 43, 43]
- percent
- [0.1, 0.1, 0.1]
config/panels/mined/64x128-64s-ls9929.toml
# generated by scripts/corpus-mine.py; regenerate rather than edit name = "64x128-64s-ls9929" [meta] status = "generates" origin = "mined" sources = 17 agreement = 0.77 examples = ["P1.875-128x64-64S-9929+9739-5.0-75B.rcvbp", "P1.875_128x64_64s-9929+9739.rcvbp", "P2.5-128x64-64S-9929+9737(mini)-3.15-_128x1024-75E_.rcvbp"] vendors = ["Colorlight"] [module] width = 64 height = 128 scan = 64 line_dir = 0 data_groups = 0 serial_clock = 14 [screen] width = 64 height = 128 [chip] library = "config/chips/mined/ls9929.toml" [current] gains = [43, 43, 43, 43] percent = [0.1, 0.1, 0.1] [mapping] reversed_groups = true reversed_lines = false block = 64 [boot] arm_at_boot = true