160x80 1/40 LS9930
160x80, 1/40 scan, LS9930, rcvbp
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Module
entry
- file
- config/panels/mined/160x80-40s-ls9930.toml
- status
- generates
- origin
- mined
- vendor files
- 4
- agreement
- 0.67
- vendors
- Colorlight
- examples
- P2-160x80-40S-9930+9736-S-one-way input.rcvbp P2-160x80-40S-9930+9736-V6.2.rcvbp P2-160x80-40S-9930+9736-V6.2.rcvbp
- notes
- the pixel map has 6400 entries; the block-7 image builder packs at most 4096, so `rxp config gen` writes the .rcvbp but not the boot image
chip
- name
- LS9930 (mined)
- library
- config/chips/mined/ls9930.toml
spec
- name
- 160x80-40s-ls9930
module
- width
- 160
- height
- 80
- scan
- 40
- line_dir
- 0
- data_groups
- 0
- serial_clock
- 16
screen
- width
- 160
- height
- 80
Wiring
mapping
- reversed_groups
- true
- reversed_lines
- false
- block
- 160
boot
- arm_at_boot
- true
Timing
current
- gains
- [43, 43, 43, 43]
- percent
- [0.1, 0.1, 0.1]
config/panels/mined/160x80-40s-ls9930.toml
# generated by scripts/corpus-mine.py; regenerate rather than edit name = "160x80-40s-ls9930" [meta] status = "generates" origin = "mined" sources = 4 agreement = 0.67 examples = ["P2-160x80-40S-9930+9736-S-one-way input.rcvbp", "P2-160x80-40S-9930+9736-V6.2.rcvbp", "P2-160x80-40S-9930+9736-V6.2.rcvbp"] vendors = ["Colorlight"] notes = "the pixel map has 6400 entries; the block-7 image builder packs at most 4096, so `rxp config gen` writes the .rcvbp but not the boot image" [module] width = 160 height = 80 scan = 40 line_dir = 0 data_groups = 0 serial_clock = 16 [screen] width = 160 height = 80 [chip] library = "config/chips/mined/ls9930.toml" [current] gains = [43, 43, 43, 43] percent = [0.1, 0.1, 0.1] [mapping] reversed_groups = true reversed_lines = false block = 160 [boot] arm_at_boot = true